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SN74AHC74QPWRG4Q1
SN74AHC74QPWRG4Q1
815-SN74AHC74QPWRG4Q1
14-TSSOP (0.173, 4.40mm Width)
2V~5.5V 115MHz D-Type Flip Flop DUAL 74AHC74 14 Pins 2μA Automotive, AEC-Q100, 74AHC Series 14-TSSOP (0.173, 4.40mm Width)
In Stock : 1923
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Product Details
Purchasing and Inquiry
SN74AHC74QPWRG4Q1 Overview
The flip flop is packaged in a case of 14-TSSOP (0.173, 4.40mm Width). It is contained within the Tape & Reel (TR)package. T flip flop uses Differentialas the output. Positive Edgeis the trigger it is configured with. It is mounted in the way of Surface Mount. A supply voltage of 2V~5.5V is required for operation. -40°C~125°C TAis the operating temperature. The type of this D latch is D-Type. In FPGA terms, D flip flop is a type of Automotive, AEC-Q100, 74AHCseries FPGA. A frequency of 115MHzshould be the maximum output frequency. T flip flop consumes 2μA quiescent energy. The number of terminations is 14. This D latch belongs to the family of 74AHC74. The power supply voltage is 3.3V. The input capacitance of this JK flip flopis 2pF farads. In this case, the D flip flop belongs to the AHC/VHC/H/U/Vfamily. It is mounted in the way of Surface Mount. It is designed with 14 pins. This device's clock edge trigger type is Positive Edge. The RS flip flops belongs to FF/Latches base part number. It reaches 5.5Vwhen the supply voltage is maximal (Vsup). The supply voltage (Vsup) should be maintained above 2V for normal operation. Using 2 circuits, it is highly flexible. As a result of its reliable performance, this T flip flop is suitable for TR. With a current output of 8mA , it offers maximum design flexibility. It has 1 output lines to operate.
SN74AHC74QPWRG4Q1 Features
Tape & Reel (TR) package
Automotive, AEC-Q100, 74AHC series
14 pins
SN74AHC74QPWRG4Q1 Applications
There are a lot of Texas Instruments SN74AHC74QPWRG4Q1 Flip Flops applications.
- Balanced 24 mA output drivers
- Shift registers
- Supports Live Insertion
- Latch
- Control circuits
- Guaranteed simultaneous switching noise level
- Communications
- High Performance Logic for test systems
- Balanced Propagation Delays
- Parallel data storage
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SN74AHC74QPWRG4Q1
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